LIBPFM(3)

NAME
libpfm_intel_adl_grt - support for Intel Alderlake Gracemont (P-core) core PMU

SYNOPSIS
#include <perfmon/pfmlib.h>

PMU name: adl_grt
PMU desc: Intel Alderlake Goldencove (E-core)

DESCRIPTION
The library supports the Intel Alderlake Gracemont (E-core) core PMU. It should be noted that this PMU model only covers each core's PMU and not the socket level PMU. Because the processor uses a hybrid architecture with a P-Core and E-Core with a different PMU model, it may be necessary to force a PMU instance name to get the desired encoding. For instance, to encode for the P-Core adl_grt::BR_INST_RETIRED and for the E-core adl_grt::BR_INST_RETIRED. On Adlerlake Gracemont (P-Core), there are 6 generic counters and 3 fixed counters. The pfm_get_pmu_info() function returns the maximum number of generic counters in num_cntrs.

MODIFIERS
The following modifiers are supported on Intel SapphireRapid processors:

u   Measure at user level which includes privilege levels 1, 2, 3. This corresponds to PFM_PLM3. This is a boolean modifier.

k   Measure at kernel level which includes privilege level 0. This corresponds to PFM_PLM0. This is a boolean modifier.

i   Invert the meaning of the event. The counter will now count cycles in which the event is not occurring. This is a boolean modifier

e   Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. This is a boolean modifier.

c   Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. This is an integer modifier with values in the range [0:255].

ldlat
    Pass a latency threshold in core cycles to the MEM_TRANS_RETIRED:LOAD_LATENCY event. This is an integer attribute that must be in the range [1:65535]. It is required for this event. The library provides a set of presets for specific latencies, such as 128. Note that the event must be used with precise sampling (PEBS).

OFFCORE_RESPONSE events
Intel Alderlake Gracemont (E-Core) supports two encodings for offcore_response events (0x1b7, 0x2b7). In the library, these are called OCR0 and OCR1. The two encodings are equivalent. On Linux, the kernel can schedule any OCR encoding into any of the two OCR counters. The offcore_response events are exposed as a normal events by the library. The extra settings are exposed as regular umasks. The library takes care of encoding the events according to the underlying kernel interface. On Intel Alderlake Gracemont (E-Core), the event is treated as a regular event with a flat set of umasks to choose from. It is not possible to combine the various requests, supplier, snoop bits anymore. The library offers the list of validated combinations as per Intel's official event list.

AUTHORS
Stephane Eranian <eranian@gmail.com>